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74F841/842/843/845/846 bus interface latches product specification replaces datasheet 74F841/842/843/844/845/846 of 1999 jan 08 ic15 data handbook 1999 jun 23 integrated circuits
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 74F841/74f842 10-bit bus interface latches, non-inverting/inverting (3-state) 74f843 9-bit bus interface latch, non-inverting (3-state) 74f845/74f846 8-bit bus interface latches, non-inverting/inverting (3-state) 2 1999 jun 23 8531208 21851 features ? high speed parallel latches ? extra data width for wide address/data paths or buses carrying parity ? high impedance npn base input structure minimizes bus loading ? iil is 20 m a vs 1000a for am29841 series ? buffered control inputs to reduce ac effects ? ideal where high speed, light loading, or increased fan-in are required as with mos microprocessors ? positive and negative over-shoots are clamped to ground ? 3-state outputs glitch free during power-up and power-down ? 48ma sink current ? slim dual in-line 300 mil package ? broadside pinout ? pin-for-pin and function compatible with amd am29841-846 series type typical propagation delay typical supply current (total) 74F841, 74f842 5.5ns 60ma 74f843, 74f845 5.5ns 75ma 74f846 6.2ns 60ma description the 74F84174f846 bus interface latch series are designed to provide extra data width for wider address/data paths of buses carrying parity. the 74F84174f846 series are funcitonally an pin compatible to the amd am29841am29846 series. the 74F841 consists of ten d-type latches with 3-state outputs. the flip-flops appear transparent to the data when latch enable (le) is high. this allows asynchronous operation, as the output transition follows the data in transition. on the le high-to-low transition, the data that meets the setup and hold time is latched. data appears on the bus when the output enable (oe ) is low. when oe is high the output is in the high-impedance state. the 74f842 is the inverted output version of the 74F841. the 74f843 consists of nine d-type latches with 3-state outputs. in addition to the le and oe pins, the 74f843 has a master reset (mr ) pin and preset (pre ) pin. these pins are ideal for parity bus interfacing in high performance systems. when mr is low, the outputs are low if oe is low. when mr is high, data can be entered into the latch. when pre is low, the outputs are high, if oe is low, pre overrides mr . the 74f845 consists of eight d-type latches with 3-state outputs. in addition to the le, oe , mr and pre pins, the 74f845 has two addtitional oe pins making a total of three output enables (oe 0, oe 1, oe 2) pins. the multiple ouptut enables (oe 0, oe 1, oe 2) allow multi-user control of the interface, e.g., cs , dma, and rd/wr . the 74f846 is the inverted output version of the 74f845. ordering information packages commercial range v cc = 5v 10%; t amb = 0 c to +70 c package drawing number 24-pin plastic slim dip (300 mil) n74F841n, n74f842n, n74f843n, n74f845n, n74f846n sot222-1 24-pin plastic sol n74F841d, n74f842d, n74f843d, n74f845d, n74f846d sot137-1 input and output loading and fan-out table pins description 74f(u.l.) high/low load value high/low dn data inputs 1.0/0.033 20 m a/20 m a le latch enable input 1.0/0.033 20 m a/20 m a oe , oe n output enable input (active low) 1.0/0.033 20 m a/20 m a mr master reset input (active low) 1.0/0.033 20 m a/20 m a pre preset input (active low) 1.0/0.033 20 m a/20 m a qn data outputs 1200/80 24ma/48ma q n data outputs 1200/80 24ma/48ma note: one (1.0) fast unit load is defined as: 20 m a in the high state and 0.6ma in the low state.
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 3 pin configuration for 74F841 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 oe d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 v cc q0 q1 q2 q3 q4 q5 q7 q6 q8 q9 le gnd sf01279 logic symbol for 74F841 13 2 sf01280 3456 78910 1 d0 le d1 d2 d3 d4 d5 d6 d7 d8 oe v cc = pin 24 gnd = pin 12 11 d9 23 22 21 20 19 18 17 16 15 14 q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 logic symbol (ieee/iec) for 74F841 1 15 18 19 20 21 23 2 1 d sf01281 16 17 5 6 7 8 9 10 4 13 en c1 22 3 14 11 pin configuration for 74f842 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 oe d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 v cc q 0 q 1 q 2 q 3 q 4 q 5 q 7 q 6 q 8 q 9 le gnd sf01282 logic symbol for 74f842 13 2 sf01283 3456 78910 1 d0 le d1 d2 d3 d4 d5 d6 d7 d8 oe v cc = pin 24 gnd = pin 12 11 d9 23 22 21 20 19 18 17 16 15 14 q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 logic symbol (ieee/iec) for 74f842 1 15 18 19 20 21 23 2 1 d sf01284 16 17 5 6 7 8 9 10 4 13 en c1 22 3 14 11
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 4 pin configuration for 74f843 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 oe d0 d1 d2 d3 d4 d5 d6 d7 d8 mr v cc q0 q1 q2 q3 q4 q5 q7 q6 q8 pre le gnd sf01285 logic symbol for 74f843 13 2 sf01286 3456 78910 d0 le d1 d2 d3 d4 d5 d6 d7 d8 v cc = pin 24 gnd = pin 12 23 22 21 20 19 18 17 16 15 q0 q1 q2 q3 q4 q5 q6 q7 q8 14 pre 11 mr 1oe logic symbol (ieee/iec) for 74f843 1 15 18 19 20 21 23 2 1 d sf01287 16 17 5 6 7 8 9 10 4 11 14 13 en r c1 s2 22 3
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 5 pin configuration for 74f845 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 oe 0 oe 1 d0 d1 d2 d3 d4 d5 d6 d7 mr v cc oe 2 q0 q1 q2 q3 q4 q6 q5 q7 pre le gnd sf01291 logic symbol for 74f845 13 sf01292 3456 78910 d0 le d1 d2 d3 d4 d5 d6 d7 v cc = pin 24 gnd = pin 12 22 21 20 19 18 17 16 15 q0 q1 q2 q3 q4 q5 q6 q7 14 pre 11 mr 1 oe0 2 oe1 23 oe2 logic symbol (ieee/iec) for 74f845 1 15 18 19 20 21 22 3 1 d sf01293a 16 17 5 6 7 8 9 10 4 2 23 14 s2 11 r 13 c1 & en pin configuration for 74f846 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 oe 0 oe 1 d0 d1 d2 d3 d4 d5 d6 d7 mr v cc oe 2 q 0 q 1 q 2 q 3 q 4 q 6 q 5 q 7 pre le gnd sf01294 logic symbol for 74f846 13 sf01295 3456 78910 d0 le d1 d2 d3 d4 d5 d6 d7 v cc = pin 24 gnd = pin 12 22 21 20 19 18 17 16 15 q0 q1 q2 q3 q4 q5 q6 q7 14 pre 11 mr 1 oe0 2 oe1 23 oe2 logic symbol (ieee/iec) for 74f846 1 15 18 19 20 21 22 3 1 d sf01296a 16 17 5 6 7 8 9 10 4 2 23 14 s2 11 r 13 c1 & en
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 6 logic diagram for 74F841 1 oe v cc = pin 24 gnd = pin 12 lq d q0 23 13 le d0 2 lq d q1 22 d1 3 lq d q2 21 d2 4 lq d q3 20 d3 5 lq d q4 19 d4 6 lq d q5 18 d5 7 lq c d q6 17 d6 8 lq d q7 16 d7 9 lq d q8 15 d8 10 lq d q9 14 d9 11 sf01297 logic diagram for 74f842 1 oe v cc = pin 24 gnd = pin 12 lq d q 0 23 13 le d0 2 lq d q 1 22 d1 3 lq d q 2 21 d2 4 lq d q 3 20 d3 5 lq d q 4 19 d4 6 lq d q 5 18 d5 7 lq c d q 6 17 d6 8 lq d q 7 16 d7 9 lq d q 8 15 d8 10 lq d q 9 14 d9 11 sf01298 function table for 74F841 and 74f842 inputs outputs inputs 74F841 74f842 operating mode oe le dn qn q n l h l l h trans p arent l h h h l transparent l l l h latched l h h l latched h x x z z high impedance l l x nc nc hold h = high voltage level l = low voltage level h = high state one setup time before the high-to-low le transition l = low state one setup time before the high-to-low le transition = high-to-low transition x = don't care nc= no change z = high impedance aoffo state
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 7 logic diagram for 74f843 1 oe v cc = pin 24 gnd = pin 12 lq c dp q0 23 13 le 11 mr 14 pre d0 2 lq c dp q1 22 d1 3 lq c dp q2 21 d2 4 lq c dp q3 20 d3 5 lq c dp q4 19 d4 6 lq c dp q5 18 d5 7 lq c dp q6 17 d6 8 lq c dp q7 16 d7 9 lq c dp q8 15 d8 10 sf01299 function table for 74f843 inputs outputs inputs 74f843 operating mode oe pre mr le dn qn l l x x x h preset l h l x x l clear l h h h l l trans p arent l h h h h h transparent l h h l l latched l h h h h latched h x x x x z high impedance l h h l x nc hold h = high voltage level l = low voltage level h = high state one setup time before the high-to-low le transition l = low state one setup time before the high-to-low le transition = high-to-low transition x = don't care nc= no change z = high impedance aoffo state
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 8 logic diagram for 74f845 1 2 23 oe 0 oe 1 oe 2 v cc = pin 24 gnd = pin 12 lq c dp q0 22 13 le 11 mr 14 pre d0 3 lq c dp q1 21 d1 4 lq c dp q2 20 d2 5 lq c dp q3 19 d3 6 lq c dp q4 18 d4 7 lq c dp q5 17 d5 8 lq c dp q6 16 d6 9 lq c dp q7 15 d7 10 sf01301 logic diagram for 74f846 1 2 23 oe 0 oe 1 oe 2 v cc = pin 24 gnd = pin 12 lq c dp q 0 22 13 le 11 mr 14 pre d0 3 lq c dp q 1 21 d1 4 lq c dp q 2 20 d2 5 lq c dp q 3 19 d3 6 lq c dp q 4 18 d4 7 lq c dp q 5 17 d5 8 lq c dp q 6 16 d6 9 lq c dp q 7 15 d7 10 sf01302 function table for 74f845 and 74f846 inputs outputs inputs 74f845 74f846 operating mode oe pre mr le dn qn q n l l x x x h h preset l h l x x l l clear l h h h l l h trans p arent l h h h h h l transparent l h h l l h latched l h h h h l latched h x x x x z z high impedance l h h l x nc nc hold h = high voltage level l = low voltage level h = high state one setup time before the high-to-low le transition l = low state one setup time before the high-to-low le transition = high-to-low transition x = don't care nc= no change z = high impedance aoffo state
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 9 absolute maximum ratings operation beyond the limits set forth in this table may impair the useful life of the device. unless otherwise noted these limits are over the operating free-air temperature range. symbol parameter rating unit v cc supply voltage 0.5 to +7.0 v v in input voltage 0.5 to +7.0 v i in input current 30 to +5 ma v out voltage applied to output in high output state 0.5 to v cc v i out current applied to output in low output state 84 ma t amb operating free-air temperature range 0 to +70 c t stg storage temperature range 65 to +150 c recommended operating conditions symbol parameter limits unit symbol parameter min nom max unit v cc supply voltage 4.5 5.0 5.5 v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i ik input clamp current 18 ma i oh high-level output current 24 ma i ol low-level output current 48 ma t amb operating free-air temperature range 0 +70 c
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 10 dc electrical characteristics over recommended operating free-air temperature range unless otherwise noted. symbol parameter test conditions 1 limits unit symbol parameter test conditions 1 min typ 2 max unit i o = 15ma 10%v cc 2.2 v v o high level out p ut voltage v cc = min, i oh = 15ma 5%v cc 2.2 3.3 v v oh high - le v el o u tp u t v oltage cc , v il = max, v ih = min i o = 24ma 10%v cc 2.0 v i oh = 24ma 5%v cc 2.0 v v o low level out p ut voltage v cc = min, i ol = 32ma 10%v cc 0.38 0.55 v v ol lo w- le v el o u tp u t v oltage cc , v il = max, v ih = min i ol = 48ma 5%v cc 0.38 0.55 v v ik input clamp voltage v cc = min, i i = i ik 0.73 1.2 v i i input current at maximum input voltage v cc = 0.0v, v i = 7.0v 100 m a i ih high-level input current v cc = max, v i = 2.7v 20 m a i il low-level input current v cc = max, v i = 0.5v 20 m a i ozh off-state output current, high-level voltage applied v cc = max, v o = 2.7v 50 m a i ozl off-state output current, low-level voltage applied v cc = max, v o = 0.5v 50 m a i os short-circuit output current 3 v cc = max 100 225 ma i cch 50 65 ma 74F841 i ccl v cc = max 60 80 ma i ccz 70 92 ma i cch 40 60 ma 74f842 i ccl v cc = max 65 90 ma i cc supply current i ccz 60 90 ma i cc y (total) i cch 65 90 ma 74f843 74f845 i ccl v cc = max 75 100 ma 74f845 i ccz 85 115 ma i cch 50 70 ma 74f846 i ccl v cc = max 70 95 ma i ccz 70 95 ma notes: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions for the applic able type. 2. all typical values are at v cc = 5v, t amb = 25 c. 3. not more than one output should be shorted at a time. for testing i os , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. otherwise, prol onged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. in any sequence of parameter test, i os tests should be performed last.
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 11 ac electrical characteristics for 74F841/74f842 limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test v cc = +5.0v v cc = +5.0v 10% unit condition c l = 50pf, r l = 500 w c l = 50pf, r l = 500 w min typ max min max t plh t phl propagation delay dn to qn 74F841 waveform 1, 2 2.0 2.5 4.0 4.5 7.5 7.5 2.0 2.5 8.0 8.0 ns t plh t phl propagation delay le to qn 74F841 waveform 1, 2 4.5 4.0 6.5 6.0 9.5 9.0 4.0 3.5 10.0 9.5 ns t plh t phl propagation delay dn to q n 74f842 waveform 1, 2 3.5 3.0 5.5 5.0 8.5 8.0 4.5 4.0 9.0 8.5 ns t plh t phl propagation delay le to q n 74f842 waveform 1, 2 5.0 4.5 7.0 6.5 10.0 9.0 3.0 3.0 10.5 9.5 ns t pzh t pzl output enable time high or low-level oe n to qn or q n waveform 5 waveform 6 2.5 4.0 4.5 6.0 8.0 9.5 2.0 3.0 8.5 10.5 ns t phz t plz output disable time high or low-level oe n to qn or q n waveform 5 waveform 6 1.0 1.0 4.5 5.0 8.0 8.0 1.0 1.0 8.5 8.5 ns ac setup requirements for 74F841/74f842 limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test v cc = +5.0v v cc = +5.0v 10% unit condition c l = 50pf, r l = 500 w c l = 50pf, r l = 500 w min typ min max t s (h) t s (l) setup time, high or low dn to le waveform 4 0.0 0.0 1.0 1.0 ns t h (h) t h (l) hold time, high or low dn to le 74F841 waveform 4 2.5 3.0 3.0 4.0 ns t w (h) le pulse width, high waveform 4 3.5 4.0 ns t h (h) t h (l) hold time, high or low dn to le 74f842 waveform 4 3.0 3.5 3.5 4.5 ns t w (h) le pulse width, high waveform 4 3.0 3.0 ns
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 12 ac electrical characteristics for 74f843/74f845 limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test v cc = +5.0v v cc = +5.0v 10% unit condition c l = 50pf, r l = 500 w c l = 50pf, r l = 500 w min typ max min max t plh t phl propagation delay dn to qn waveform 1, 2 2.0 2.5 4.5 4.5 7.5 8.0 2.0 2.5 8.5 8.5 ns t plh t phl propagation delay le to qn waveform 1, 2 4.5 4.0 6.5 6.0 9.5 8.5 4.5 4.0 10.0 8.5 ns t plh propagation delay pre to qn waveform 3 3.5 5.5 8.5 3.0 9.0 ns t phl propagation delay mr to qn waveform 3 2.0 4.5 7.5 2.0 8.0 ns t pzh t pzl output enable time high or low-level oe n to qn waveform 5 waveform 6 2.5 4.0 4.5 6.0 7.5 9.5 2.0 3.0 8.0 10.5 ns t phz t plz output disable time high or low-level oe n to qn waveform 5 waveform 6 1.0 1.0 4.5 5.0 8.0 8.0 1.0 1.0 8.5 8.5 ns ac setup requirements for 74f843/74f845 limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test v cc = +5.0v v cc = +5.0v 10% unit condition c l = 50pf, r l = 500 w c l = 50pf, r l = 500 w min typ min max t s (h) t s (l) setup time, high or low dn to le waveform 4 1.0 1.0 0.0 0.0 ns t h (h) t h (l) hold time, high or low dn to le waveform 4 3.0 4.0 3.0 4.0 ns t w (h) le pulse width, high waveform 4 3.0 3.0 ns t w (l) pre pulse width, low waveform 3 4.0 5.0 ns t w (h) mr pulse width, low waveform 3 4.0 5.0 ns t rec pre recovery time waveform 3 0.0 0.0 ns t rec mr recovery time waveform 3 3.5 4.5 ns
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 13 ac electrical characteristics for 74f846 limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test v cc = +5.0v v cc = +5.0v 10% unit condition c l = 50pf, r l = 500 w c l = 50pf, r l = 500 w min typ max min max t plh t phl propagation delay dn to q n waveform 1, 2 3.5 3.0 5.5 5.0 8.5 8.0 3.0 3.0 9.5 8.5 ns t plh t phl propagation delay le to q n waveform 1, 2 5.0 4.5 7.0 6.5 10.0 9.0 5.0 4.5 10.5 9.5 ns t plh propagation delay pre to q n waveform 3 3.5 5.5 8.5 3.0 9.5 ns t phl propagation delay mr to q n waveform 3 5.0 7.0 10.0 4.5 10.5 ns t pzh t pzl output enable time high or low-level oe n to q n waveform 5 waveform 6 2.5 4.0 5.0 6.0 7.5 9.5 2.0 3.0 8.0 10.5 ns t phz t plz output disable time high or low-level oe n to q n waveform 5 waveform 6 1.0 1.0 4.5 5.0 8.0 8.0 1.0 1.0 8.5 8.5 ns ac setup requirements for 74f846 limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test v cc = +5.0v v cc = +5.0v 10% unit condition c l = 50pf, r l = 500 w c l = 50pf, r l = 500 w min typ min max t s (h) t s (l) setup time, high or low dn to le waveform 4 0.0 0.0 0.0 0.0 ns t h (h) t h (l) hold time, high or low dn to le waveform 4 3.0 4.0 3.0 4.0 ns t w (h) le pulse width, high waveform 4 3.0 3.0 ns t w (l) pre pulse width, low waveform 3 4.0 5.0 ns t w (h) mr pulse width, low waveform 3 4.0 5.0 ns t rec pre recovery time waveform 3 0.0 0.0 ns t rec mr recovery time waveform 3 3.5 4.5 ns
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 14 ac waveforms for all waveforms, v m = 1.5v. the shaded areas indicate when the input is permitted to change for predictable output performance. v m v m v m v m t phl t plh dn, le qn sf01303 waveform 1. propagation delay, non-inverting path v m v m v m v m t plh t phl dn, le q n sf01304 waveform 2. propagation delay, inverting path le v m v m pre , mr v m t w (l) t rec v m v m t plh t phl qn, q n qn, q n sf01305 waveform 3. master reset and preset pulse width, master reset and preset to output delay, and master reset and preset to latch enable recovery time t h (h) t s (h) le v m v m v m v m v m v m t h (l) t s (l) dn v m t w (h) sf01306 waveform 4. data setup and hold times v m v m v m t phz t pzh oe n v oh -0.3v 0v qn, q n sf00509 waveform 5. 3-state output enable time to high level and output disable time from high level v m v m v m t plz t pzl v ol +0.3v 3.5v oe n qn, q n sf00510 waveform 6. 3-state output enable time to low level and output disable time from low level
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 15 test circuit and waveforms t w 90% v m 10% 90% v m 10% 90% v m 10% 90% v m 10% negative pulse positive pulse t w amp (v) 0v 0v t thl ( t f ) input pulse requirements rep. rate t w t tlh t thl 1mhz 500ns 2.5ns 2.5ns input pulse definition v cc family 74f d.u.t. pulse generator r l c l r t v in v out test circuit for 3-state outputs definitions: r l = load resistor; see ac electrical characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac electrical characteristics for value. r t = termination resistance should be equal to z out of pulse generators. t thl ( t f ) t tlh ( t r ) t tlh ( t r ) amp (v) amplitude 3.0v 1.5v v m r l 7.0v sf00777 test switch t plz closed t pzl closed all other open switch position
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 16 dip24: plastic dual in-line package; 24 leads (300 mil) sot222-1
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 17 so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1
philips semiconductors product specification 74F841/74f842/74f843/ 74f845/74f846 bus interface latches 1999 jun 23 18 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1999 all rights reserved. printed in u.s.a. date of release: 06-99 document order number: 9397 750 06143

data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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